This research addresses absorptive capacity in maintaining technological advantage amidst Emerging and Disruptive Technologies (EDTs). While traditional models focus on incremental integration, this study introduces the construct of transformative capability to account for the systemic reconfiguration necessitated by Artificial Intelligence and Big Data as two out of nine EDTs. Utilizing a structured policy research methodology, the study evaluates a purposive sample of 56 NATO policy documents, triangulated with semi-structured stakeholder interviews to identify high-priority catalysts for adoption. Findings identify four interconnected factors—technological, human, organizational, and societal—functioning as a recursive, systemic feedback loop. A distinctive contribution is the identification of the psychological unimaginability of EDTs as a primary barrier to diffusion, necessitating cognitive anchors through robust standardization, ethical governance and social institutionalization. By positioning ethics and societal assimilation as functional prerequisites, this research offers a multidimensional framework for fostering double-loop learning and organizational resilience in 21st-century defense ecosystems. 

Huawei introduced the Tau (τ) Scaling Law at the 2026 IEEE International Symposium on Circuits and Systems, presenting a transformative approach to semiconductor evolution. As Moore's Law faces physical and economic limitations, this new principle replaces traditional geometric scaling with time-based scaling to guide future semiconductor development. Leveraging innovative technologies such as LogicFolding and multi-level co-optimization mechanisms spanning devices, circuits, chips, and systems, the τ Scaling Law systematically reduces time constants to enhance performance, energy efficiency, and transistor density. This approach addresses the semiconductor industry's critical challenge of overcoming physical constraints while meeting escalating computing demands, offering a sustainable path forward for continued technological advancement.

TSMC has been pioneering advanced 3D packaging, chiplet stacking, and hybrid bonding for nearly a decade. Huawei is simply applying these existing concepts ...

Huawei has announced an ambitious semiconductor roadmap targeting 1.4-nanometer chip design by 2031, as revealed by HiSilicon President He Tingbo at the 2026 IEEE ISCAS conference in Shanghai. To circumvent U.S. technology sanctions restricting access to advanced EUV lithography equipment, Huawei introduced the Tau Scaling Law, which prioritizes system-level efficiency and latency reduction over traditional geometric transistor scaling. The company's LogicFolding architecture optimizes internal interconnects and silicon stacking to achieve performance equivalent to advanced nodes without requiring cutting-edge lithography. This strategic pivot represents China's significant effort to maintain semiconductor independence while advancing chip capabilities under strict export restrictions.

Computational lithography, transistor simulation, process control and wafer inspection now require massive-scale simulation and real-time optimization, and AI ...

On May 25, 2026, Huawei presented LogicFolding, a novel 3D chip architecture designed to circumvent dependence on EUV lithography technology. Unveiled by semiconductor division president He Tingbo at the IEEE ISCAS conference, this approach claims 55% superior transistor density compared to conventional planar designs through temporal scaling rather than geometric scaling. The technology targets equivalence to 1.4-nanometer processes by 2031 via architectural innovation rather than advanced etching. Huawei expects first Kirin chips featuring LogicFolding by fall 2026, with plans to extend the technology to Ascend AI accelerators by 2030. While the company claims six years of development and mass production of 381 chips, these claims remain unverified. The announcement triggered a 7.6% stock surge for Chinese foundry SMIC, reflecting industry confidence in potential alternatives to restricted advanced manufacturing capabilities.

In 1932, American industrialist Eben Byers died after his jaw physically collapsed from drinking “Radithor”, an over-the-counter energy drink infused with raw radium. In the early 20th century, society was so mesmerized by the superficial “glow” of radiation that brands blindly put thorium and radium into cosmetics, toothpaste, and water. It wasn’t until 1938, when the lethal, cellular-level destruction of radiation became undeniable, that governments stepped in, stripped radioactive elements from consumer shelves, and locked nuclear energy behind strict regulatory walls.Today, we are repeating that exact historical error.

NVIDIA and TSMC are leveraging artificial intelligence and accelerated computing to revolutionize semiconductor manufacturing. NVIDIA's CUDA-X libraries, Metropolis platform, and TAO Toolkit are being deployed across TSMC's production operations to enhance lithography simulation, transistor modeling, process control, and wafer inspection. These advanced AI systems enable automated defect detection at the nanometer scale while reducing manual labeling requirements. By integrating AI throughout the semiconductor design and manufacturing lifecycle, TSMC achieves improved turnaround times, enhanced energy efficiency, increased yield rates, and optimized fab operations. This collaboration between the two technology leaders addresses complex computational challenges inherent in advancing chip production to increasingly sophisticated nodes.

NVIDIA and TSMC are leveraging accelerated computing and artificial intelligence to revolutionize semiconductor design and manufacturing processes. As chip technology advances to more complex nodes, the industry faces unprecedented computational challenges in areas including computational lithography, transistor simulation, process control, and wafer inspection. TSMC is deploying NVIDIA's AI and accelerated computing solutions across its fab operations to enhance turnaround times, energy efficiency, yield rates, and overall operational productivity. This strategic partnership, spanning nearly three decades, represents a significant advancement in addressing the world's most complex design and manufacturing challenges through simulation, optimization, and AI-driven systems capable of supporting physics-based and image analysis applications simultaneously.

Photonics represents a transformative frontier in advancing next-generation optical communication networks. This open-access perspective article, published in May 2026, explores emerging technologies and innovations that leverage photonic principles to enhance data transmission capabilities. The research examines how photonic systems can address current limitations in optical communications, enabling faster, more efficient information transfer. By integrating cutting-edge photonic solutions, these networks promise substantial improvements in bandwidth capacity and system reliability. The article provides valuable insights for professionals seeking to understand the technological evolution of communication infrastructure and its implications for future digital connectivity.

Quantum networks represent a transformative technological advancement that harnesses quantum mechanical principles to revolutionize data transmission and computational capacity. Unlike classical systems using binary bits, quantum networks employ quantum bits or qubits, which exploit superposition to exist in multiple states simultaneously, and leverage entanglement to create instantaneous connections across distances. By linking quantum computers and ultraprecise sensors, these networks enable geographically distributed systems to operate in concert, delivering unprecedented measurement accuracy and processing power. Applications span earthquake prediction, agricultural monitoring, autonomous GPS-free navigation for emergency responders in challenging environments, and accelerated drug discovery through molecular simulation. Quantum networks fundamentally transcend the limitations of conventional binary-based architectures, offering transformative potential for scientific discovery and practical problem-solving across multiple sectors.

Huawei has unveiled the Tau Scaling Law and LogicFolding architecture, representing China's ambitious response to US chip export restrictions. Rather than pursuing traditional transistor miniaturization governed by Moore's Law, this framework shifts focus to time scaling—compressing signal travel duration through chips and systems. Presented by Huawei's semiconductor president at the 2026 IEEE symposium, the approach operates across four integrated levels: device, circuit, chip, and system. LogicFolding architecture optimizes critical-path wiring and resistance while UnifiedBus reduces latency in large-scale AI deployments. Huawei claims this methodology will enable high-end chips achieving transistor density equivalent to advanced nodes, effectively circumventing lithography equipment constraints imposed by international restrictions.

C'est du jamais vu dans l'histoire de l'intelligence artificielle et un immense séisme pour la tech. Lancé lundi, désactivé jeudi soir : le gouvernement américain a ordonné à Anthropic de couper l'accès à Fable 5 et Mythos 5, ses deux modèles d'IA les plus avancés, pour l'ensemble de ses clients dans le monde entier, sur fond de faille de sécurité contestée.

Faced with an exhausted terrestrial power grid, Elon Musk is moving hyperscale AI data centers directly into Low Earth Orbit.

Medical catheters face certain challenges in clinical treatment, such as bacterial biofilm adhesion and thrombus formation. Antifouling and antibacterial coatings have been proven to be an effective solution to diminish these undesirable events. Herein, we developed a facile and environmentally friendly strategy for constructing a dual-functional coating by grafting an antibacterial-zwitterionic copolymer onto polyurethane (PU) surfaces. The copolymer was designed and synthesized via a one-pot polymerization in an aqueous system by integrating 2-methacryloyloxyethyl phosphorylcholine (MPC), dimethyl diallyl ammonium chloride (DADMAC), and glycidyl methacrylate (GMA) as a functional monomer to enable surface immobilization.

The Chinese tech giant says its new stacked-chip architecture can deliver transistor density equivalent to 1.4nm processes by 2031, without access to advanced lithography tools

Artificial intelligence presents a fundamental paradox: despite its weightless digital nature, it demands massive physical infrastructure and enormous energy consumption. Researchers from the University of Cambridge and the University at Buffalo have developed an innovative neuromorphic chip that addresses this sustainability challenge by reimagining computer architecture. Unlike conventional systems that separate processing and memory functions, this bio-inspired device simultaneously executes both operations, mirroring human brain functionality. This breakthrough, achieved after nearly three years of experimentation and countless failed attempts, represents a significant departure from classical computing design. By eliminating the inefficient data shuttling inherent in traditional hardware, the new chip offers a sustainable alternative to current systems. The innovation addresses a persistent obstacle in developing environmentally responsible artificial intelligence and demonstrates the potential for hardware design to revolutionize machine cognition while reducing energy consumption.

This paper presents a novel approach to bridging the performance gap between biological and artificial neural systems by integrating genuine neuromorphic circuits into conventional artificial neural network architectures. The research demonstrates that embedding astrocytic modulation and spiking dynamics—key features of biological neural structures—enables hybrid models to achieve remarkable capabilities. Specifically, these enhanced systems attain high accuracy from minimal training examples per class while maintaining robust performance under challenging conditions including occlusion and impulse noise. The findings suggest that incorporating biologically-inspired neuromorphic components offers a promising pathway to enhance artificial neural networks' learning efficiency and noise resilience, advancing toward achieving neuromorphic supremacy in machine learning applications.

Huawei has introduced the Tau (τ) Scaling Law, a novel semiconductor development principle presented at the 2026 IEEE International Symposium on Circuits and Systems. This groundbreaking framework proposes shifting from traditional geometric scaling to time-based scaling as the guiding principle for semiconductor and electronic system evolution. The innovation leverages advanced technologies such as LogicFolding to achieve continuous compression of signal propagation, enabling unprecedented breakthroughs in transistor density and overall system performance. This paradigm represents a significant advancement in semiconductor engineering methodology.

Huawei recently presented claims regarding its 1.4nm LogicFolding technology at an IEEE conference in March 2026, positioning it as a breakthrough in semiconductor advancement. The company argues that traditional logic scaling has reached limitations, necessitating alternative approaches to increase transistor density. However, the presentation raises significant concerns regarding the accuracy of Huawei's density calculations and the credibility of their research paper, which appears to have been generated using artificial intelligence. Industry experts question whether Huawei's claims substantively advance the field or merely represent marketing positioning ahead of competitors. The presentation introduces concepts like Tau Scaling and LogicFolding architecture, yet lacks the transparency necessary to validate technological superiority claims. These developments warrant careful scrutiny from the semiconductor intelligence community.